Design of 100 Gb/s SerDes receiver front-end based on Gm-TIA

LIU Shutao; SHAO Lei

doi:10.20193/j.ices2097-4191.2025.0098

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Integrated Circuits and Embedded Systems ›› 2026, Vol. 26 ›› Issue (2) : 63-70. DOI: 10.20193/j.ices2097-4191.2025.0098

Special Issue of the 9th China College IC Competition

Design of 100 Gb/s SerDes receiver front-end based on Gm-TIA

LIU Shutao ^* ,
SHAO Lei

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Abstract

This paper presents an analog front-end circuit for high-speed SerDes receivers, designed to address varying channel losses. Utilizing a transconductance-transimpedance (Gm-TIA) architecture, the circuit implements a continuous-time linear equalizer (CTLE) with a tunable peaking gain of 2.2~12.5 dB at the Nyquist frequency and a variable gain amplifier (VGA) with a gain range of -8~3.5 dB, offering flexibility for different channel characteristics. A complementary transconductance stage is employed to achieve current reuse, enhancing transconductance and power efficiency. A T-coil structure is designed to achieve broadband impedance matching, considering parasitics from ESD, pads, and AC-coupling. Inductive peaking and tunable MOS resistors are adopted to extend bandwidth and enable continuous gain tuning. Fabricated in a 65 nm CMOS process, post-layout simulations show that the front-end achieves a peaking gain of 1.1~11.5 dB at 25 GHz Nyquist frequency, supports 100 Gb/s PAM4 signal transmission, and consumes 12.83 mW under a 1.2 V supply.

Key words

SerDes / CTLE / VGA / Gm-TIA / CMOS

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LIU Shutao , SHAO Lei. Design of 100 Gb/s SerDes receiver front-end based on Gm-TIA[J]. Integrated Circuits and Embedded Systems. 2026, 26(2): 63-70 https://doi.org/10.20193/j.ices2097-4191.2025.0098

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