To tackle the concurrent challenges of bandwidth, linearity, and integration in the analog front-end (AFE) of a 100-Gbps PAM-4 wireline receiver for Chiplet interconnect applications, this paper presents a high-performance AFE architecture based on a transconductance–transimpedance amplifier (GM-TIA) continuous-time linear equalizer (CTLE). The proposed AFE efficiently compensates for channel loss while maintaining high linearity through an integrated broadband input matching network consisting of an asymmetric T-coil, a programmable attenuator, and an AC coupler. A two-stage cascaded GM-TIA-based CTLE enables wide-range gain tuning from low to high frequencies and also serves as a variable-gain amplifier (VGA). Designed in a 28-nm CMOS process, the AFE occupies a core area of 0.012 mm² with the power dissipation of 9.94 mW. The equalization tuning range extends from 2.25 dB to 13.39 dB. After equalization, the 100-Gbps PAM-4 output exhibits an eye height greater than 100 mV and an eye width exceeding 0.52 UI.