Front-end RTL design is a critical phase determining a chip's performance, power, and area (PPA). Conventional methodologies often prioritize functional implementation, lacking systematic optimization for PPA metrics. To address this, this paper proposes a multi-dimensional RTL optimization approach—the DCAP co-optimization model. This model establishes a framework encompassing four dimensions: Data-path (D), Computation (C), Area-management (A), and Power-management (P). Using the USB 2.0 link layer as a case study, data throughput is enhanced via a coupled handshake scheme, computational efficiency is optimized using a real-time iterative CRC architecture, area overhead is controlled through resource management, and power consumption is reduced by improving clock gating coverage. Back-end implementation results based on TSMC 65nm technology demonstrate that the design achieves a throughput of 52.3 MB/s (protocol efficiency:87%) in High-Speed mode, with a power consumption of 0.156 mW and an area of 3333.6 μm². Compared to the pre-optimized design, this represents a 39% reduction in power and a 23% reduction in area. In conclusion, the proposed DCAP model provides a reusable methodological guide for addressing PPA optimization challenges in digital circuit design at the register-transfer level.