Large Language Models (LLMs) face dual challenges in automated hardware design: ensuring functional correctness and achieving human-expert-level optimization efficiency. Circuits generated by existing models often suffer from a fundamental "Boolean optimization barrier," resulting in a gate count that is 38% to 1075% higher than human-expert designs. To address this, we introduce VeriOptima, a novel two-stage AI framework designed to bridge the gap from natural language specifications to highly-optimized gate-level netlists. The first stage, ReasoningV, is a high-fidelity Verilog generation model that ensures functional correctness through a high-quality dataset and an adaptive reasoning mechanism. Its performance was independently evaluated, achieving a 57.8% pass@1 accuracy on the VerilogEval-Human benchmark, which is competitive with top-tier state-of-the-art (SOTA) models. The second stage, CircuitMind, is a multi-agent optimization framework that takes the code generated by ReasoningV and refines it to human-competitive efficiency. For rigorous evaluation, we introduce TC-Bench, the first gate-level benchmark derived from a competitive circuit design platform. Experiments validate the effectiveness of our integrated framework. ReasoningV achieves state-of-the-art performance among open-source Verilog generation models. More critically, in comparative compilation-optimization experiments, using designs from ReasoningV as a starting point yields significantly better final Power, Performance, and Area (PPA) metrics than when starting with code from other LLMs. Ultimately, after refinement by CircuitMind, 55.6% of the implementations reach or surpass the efficiency of top human experts. This work presents the first end-to-end solution to systematically overcome the challenges of both generation and optimization, paving the way for fully automated, high-quality circuit implementation. The related code has been released on GitHub:ReasoningV（https://github.com/BUAA-CLab/ReasoningV）and CircuitMind（https://github.com/BUAA-CLab/CircuitMind）。