Design of logistics sorting robot based on domestic FPGA acceleration

LU Yuning; ZHANG He; YU Ming; REN Jiayun

doi:10.20193/j.ices2097-4191.2025.0111

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Integrated Circuits and Embedded Systems ›› 2026, Vol. 26 ›› Issue (2) : 91-99. DOI: 10.20193/j.ices2097-4191.2025.0111

Special Issue of the 9th China College IC Competition

Design of logistics sorting robot based on domestic FPGA acceleration

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Abstract

In response to the demand for high real-time motion control and multi-axis collaborative precision optimization in the intelligent development of warehouse logistics robots, a logistics sorting robot system based on domestic FPGA acceleration has been designed and implemented. The core of this system lies in hardware-level optimization of key algorithms: utilizing a customized ISP module to process and achieve sorting target recognition, combined with a hardware-accelerated CORDIC algorithm to efficiently complete inverse kinematics solution, ensuring accurate grasping by the robotic arm, employing a cascade PID algorithm integrated with Kalman filtering to generate high-precision multi-channel PWM signals, driving the mobile platform to deliver accurately. Additionally, the system integrates touchscreen human-computer interaction functions and a dual-arm collaborative handling strategy based on LoRa communication and ultrasonic ranging feedback. The experimental results show that the robotic arm's single operation cycle is optimized to 4 seconds, with a grasping accuracy rate of 90%, the mobile platform's positioning accuracy reaches the centimeter level, and the end-effector error of dual-arm collaborative handling is less than 0.5 cm. This design provides a low-cost, high-reliability domestic solution for the logistics sorting field.

Key words

logistics sorting robot / FPGA / image processing / inverse kinematics / Kalman filter / cascade PID algorithm / dual-arm collaborative handling

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LU Yuning , ZHANG He , YU Ming , et al. Design of logistics sorting robot based on domestic FPGA acceleration[J]. Integrated Circuits and Embedded Systems. 2026, 26(2): 91-99 https://doi.org/10.20193/j.ices2097-4191.2025.0111

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