This paper presents the design of a receiver AFE suitable for 100 Gb/s PAM-4 signals based on TSMC 65 nm CMOS technology. Employing a CTLE+VGA+TIA architecture, the CTLE compensates for channel loss while the VGA+TIA provides gain control. The CTLE section, incorporating a cascode structure, negative capacitance compensation, and tunable low-pass filtering, achieves a tunable gain range of 2.7 dB to 18 dB at the Nyquist frequency (25 GHz). The VGA, cascaded with an inverter-based transimpedance amplifier (TIA), enables precise gain adjustment in 1 dB steps from -3 dB to 12 dB through a 4-bit DAC. The continuous-time linear equalizer (CTLE) and variable gain amplifier (VGA) modules innovatively implement reverse-coupled inductive peaking technology to enhance bandwidth, improve gain, and optimize noise. Simultaneously, the TIA employs peaking inductor bandwidth extension and low-impedance path noise optimization techniques, extending the system's 1 dB bandwidth to 42.8 GHz while further optimizing noise. Additionally, this paper introduces a g_m-boosting-based interstage magnetic feedback technique, forming a triple-coupled inductor structure between the VGA and TIA stages, effectively enhancing overall gain. The core layout area measures 0.175 mm², and post-simulation results demonstrate that when compensating for 5/10/15 dB@25 GHz channel losses, the total power consumption remains below 18.7 mW, with root mean square noise not exceeding 1.08 mVrms. The system successfully opens previously closed eye diagrams, with all performance metrics meeting or exceeding design specifications.