Image Recognition System Based on Domestic FPGA and ASIC Structure

Chen Guanfu, Lan Xiaolei, Chen Zhencheng, Zhang Yihao, Chen Linliang, Li Sai

Integrated Circuits and Embedded Systems ›› 0

Integrated Circuits and Embedded Systems ›› 0 DOI: 10.20193/j.ices2097-4191.2025.0114

Image Recognition System Based on Domestic FPGA and ASIC Structure

  • Chen Guanfu, Lan Xiaolei, Chen Zhencheng, Zhang Yihao, Chen Linliang, Li Sai
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Abstract

Field-Programmable Gate Arrays (FPGAs) are key platforms for edge computing and have broad potential in edge-side image recognition. This paper presents an embedded system based on a domestically produced FPGA and a self-designed ASIC-like architecture for real-time edge deployment. On the software side, a lightweight neural network named NexusEdgeNet is proposed. It achieves 94.22% accuracy on 39 farmland disease categories with only 0.184 MB of parameters. On the hardware side, an ASIC-like accelerator fully described in Verilog is designed. It adopts a distributed on-chip memory structure, eliminating external memory access, and supports arbitrary-shaped convolution, pooling, and fully connected operations. Several optimization techniques are applied, including near-memory parallel computing, pipelining, sliding convolution windows, and double buffering. The accelerator reaches 399 FPS inference speed on the EP6HL130 FPGA, with 85% resource utilization and significantly reduced logic consumption. The system integrates image acquisition, processing, and display, supporting real-time video stream recognition. It maintains high accuracy while achieving excellent real-time performance and resource efficiency. This work provides a practical, low-cost solution for edge computing applications based on domestic FPGAs.

Key words

FPGA / Neural Processing Unit / Hardware Acceleration / Edge Computing / Image Recognition

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Chen Guanfu, Lan Xiaolei, Chen Zhencheng, Zhang Yihao, Chen Linliang, Li Sai. Image Recognition System Based on Domestic FPGA and ASIC Structure[J]. Integrated Circuits and Embedded Systems. 0 https://doi.org/10.20193/j.ices2097-4191.2025.0114

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