This paper presents a programmable computing-in-memory circuit based on a 4T GC-eDRAM cell, designed for cryogenic applications. First, a dual word-line readout structure is proposed to prevent data corruption in the memory cell. Second, leveraging the characteristic that computational data is often zero-biased, a zero-enhancement decoder/encoder circuit is proposed to further reduce read power consumption. Finally, a programmable near-memory computing circuit is implemented, capable of supporting both logic operations and arithmetic operations such as addition, subtraction, multiplication, and division. The design was fabricated and verified using a TSMC 65nm low power process. Experimental results demonstrate that the proposed circuit achieves a maximum speedup of 6× for convolution operations and 12.3× for lightweight data encryption. Within the temperature range of -40°C to 85°C, the circuit exhibits superior read, write and computing energy efficiency compared to a 6T SRAM structure. It is worth noting that, as this circuit is based on a GC-eDRAM design, its performance is closely linked to leakage current and refresh frequency. As the temperature is lowered further into the liquid nitrogen range (77 K), the leakage current of MOS transistors is drastically reduced, enabling the refresh cycle to be significantly extended. This maximizes the circuit's energy efficiency ratio, giving the designed circuit substantial advantages in low-temperature computing applications.