:With the increasing complexity and integration levels of integrated circuits, Diagnosis-Driven Yield Analysis (DDYA) has become increasingly important in accelerating physical failure analysis and improving yield. However, the low diagnostic resolution of scan chain diagnosis based on scan testing remains a weak link in DDYA. This thesis studies a scan chain diagnosis based on hardware architecture improvement—Sideway Scan, This technique groups scan chains through clock domain or layout constraints and introduces a cyclic shift sideway transmission path between adjacent scan chains within each group. By transmitting data from the faulty chain to the normal chain and then unloading it, followed by analysis using the sideway diagnostic algorithm, the technique enables precise diagnosis of various fault scenarios. This architecture offers lower hardware overhead compared to the two-dimensional scan and higher diagnostic resolution compared to the bidirectional scan. Comparative experiments across multiple circuits demonstrate that, compared to software-based scan chain diagnosis, Sideway Scan achieves up to 41% improvement in single-fault diagnosis resolution, up to 80% in double-fault diagnosis, and up to 168% in triple-fault diagnosis. Meanwhile, in various fault scenarios, diagnosis time is reduced by over 90%, with the maximum reduction reaching 99%. The study demonstrates the feasibility, stability, time advantage, and diagnostic resolution advantage of the sideway scan, providing a more efficient and precise solution for fault diagnosis in complex integrated circuits.