Stochastic computing (SC), an unconventional computational paradigm, employs probabilities to represent numerical values. This representation enables complex arithmetic operations to be performed using simple logic gates. This work presents a fast unary median filtering circuit design. The proposed filter utilizes counters to generate stochastic numbers (SNs) and constructs fundamental sorting network units using stochastic correlation logic. A feedback loop, formed based on the output, dynamically terminates computations early without consuming additional hardware area, significantly reducing substantial circuit latency. Experimental results demonstrate that the proposed median filter design outperforms existing implementations in both actual bitstream length and energy consumption. Specifically, the proposed 3×3 window median filter circuit achieves a 55.58% reduction in energy. Further validation using median filtering on images corrupted by salt-and-pepper noise confirms the accuracy of the proposed circuit. For a 16-input sorting network application, the proposed design exhibits lower consumption when inputs range within [0, 0.5], achieving up to a 50% reduction in actual bitstream length and energy consumption.