As integrated circuit feature sizes continue to shrink, the antenna effect increasingly impacts chip reliability. Layer assignment, a critical step in physical design, allocates 2D routing segments into a multi-layer 3D space. Improper assignment can cause wires to form excessively long antennas that accumulate charge and damage gates. However, existing research primarily focuses on delay and via optimization without adequately considering antenna effects. Moreover, the widely adopted non-default-rule (NDR) wire technology in advanced nodes exacerbates antenna effects due to larger wire widths. This paper proposes an antenna-aware layer assignment algorithm for advanced technology nodes comprising four core strategies. An antenna-cost-aware dynamic programming strategy that reduces violations during initialization. A high-layer-priority segment reassignment strategy that precisely controls antenna area growth. A timing-aware NDR replacement strategy that fixes violations while limiting delay impact. A g-edge resource negotiation strategy that releases routing resources through cross-net coordination. The experimental results demonstrate that the proposed algorithm significantly reduces antenna-violating nets and pins while maintaining excellent delay and via count performance.