Aiming at the problems such as the limited on-chip resources of the self-developed DSP (Digital Signal Processor) and the insufficient storage space for large-scale data and programs, a configurable External Memory Interface (EMIF) design scheme is proposed and designed. This scheme achieves flexible access to three types of memory, namely asynchronous memory, SDRAM and SBSRAM, through four configurable chip selection space registers, and realizes efficient data transmission between the CPU and external memory by using an enhanced direct memory access module. By writing a testbench and comparing the consistency of read data and written data, EMIF has undergone a relatively thorough functional verification. The experimental results show that this design realizes the read-write burst access of 8/16/32bit data. Under the 40nm low-power process, the area is 25,119.36μm2 and the power consumption is 1.296mW.