In compute-in-memory (CIM) employing high-density 2T0C arrays, parasitic capacitances critically determine charge redistribution and bit line integration dynamics, directly impacting storage-node (SN) disturbance and computational linearity. However, the escalating computational cost of conventional extraction methods with array size obstructs efficient array-level modeling and system analysis. To address this, we propose a high-accuracy approximation method for extracting parasitics from the central cell of large-scale arrays by leveraging the attenuating coupling of long interconnects. The method constructs a nine-port aggregated equivalent network by bundling non-adjacent word/bit lines and derives a quantitative expression for the minimum truncation distance of key capacitances under a 1% relative-error bound, enabling rapid array-level (AM) parameter extraction. This facilitates high-accuracy models for the SN and bit line capacitances (C_SN and C_RBL) across operational phases, accurately capturing the near-linear scaling of C_RBL with array size. Simulations under 10× geometric scaling show a 15% accuracy improvement over the device-level model (DM). Crucially, linearity analysis based on this precise model reveals that using the low-accuracy DM would overestimate the peak integral non-linearity (INL) by approximately 1.5 least significant bit (LSB).