Aiming at the problem that the existing FPGA matrix inversion methods are difficult to balance hardware resources, calculation delay and calculation accuracy, this paper proposes a matrix inversion architecture that integrates algorithm optimization and hardware architecture design. In this paper, based on MGS-QR decomposition, the parallel vector operations in the operation flow are integrated, and the calculation of the inverse matrix is transformed into the integration of the partial sum of each iteration in the iterative process, and the vector processing unit adaptation algorithm supporting multiple vector operation modes is designed. This architecture enables the inversion of an N×N real matrix to be accomplished using resources that grow quadratically with the matrix size and clock cycles that increase linearly with the matrix size. It is capable of adapting to the processing requirements of matrices of different sizes. Compared with the traditional MGS-QR factorization matrix inversion method, the designed architecture further reduces the amount of DSP usage and significantly shorts the calculation delay under the premise of ensuring the same calculation accuracy, which can provide an efficient and highly reliable engineering solution for real-time matrix inversion in embedded systems.