Research on Validation Methods for Reliability Data of VLSI/ULSI

zhang xiaowen

Integrated Circuits and Embedded Systems ›› 0

Integrated Circuits and Embedded Systems ›› 0 DOI: 10.20193/j.ices2097-4191.2026.0036

Research on Validation Methods for Reliability Data of VLSI/ULSI

  • zhang xiaowen
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Abstract

Targeting the characteristics of GJB/Z 299C-2006 "Reliability Prediction Handbook for Electronic Equipment," where predicted reliability data for various components, including integrated circuit chips under operational conditions, often deviate significantly from actual situations, a failure mechanism-based reliability data validation method has been designed. This validation method starts from the failure mechanisms in very large-scale integrated circuit chips and, based on an analysis of domestic and international standards for evaluating reliability related to failure mechanisms, summarizes the failure physics models in national standards. Leveraging reliability test structures, through accelerated life testing for single failure mechanisms, the median time to failure for primary failure mechanisms is derived. By converting the median time to failure into failure rates, reliability data for very large-scale integrated circuits is obtained, ensuring the validity of the reliability data from a physical mechanism. These reliability data can be applied to the reliable utilization of avionics products while also supporting reliability prediction work for electronic products.

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GJB/Z 299C-2006 / ULSI/VLSI / reliability datum / failure physics model / accelerate lifetime experiment / lifetime

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zhang xiaowen. Research on Validation Methods for Reliability Data of VLSI/ULSI[J]. Integrated Circuits and Embedded Systems. 0 https://doi.org/10.20193/j.ices2097-4191.2026.0036

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