QuestaSIM/ModelSIM serves as a prevalent simulation platform for FPGA verification, where workflow automation has demonstrated substantial efficacy in enhancing verification productivity. The canonical simulation flow of QuestaSim/ModelSim comprises six sequential stages: compilation, optimization, design elaboration and loading into the VSIM kernel, execution and debugging, context preservation, and platform termination. Contemporary automation scripts predominantly leverage primitive commands documented in the QuestaSim/ModelSim Command Reference Manual to mechanize this pipeline in a batch-processing manner. Switching between different testcases under the existing simulation workflow script necessitates exiting the QuestaSim/ModelSim platform, modifying the script to select the target testcase, and then repeating the entire workflow. Executing a large number of testcases necessitates frequent launches and exits of the simulation platform. Moreover, the current workflow lacks a dedicated error-handling procedure for common simulation-time errors. To address these issues, this paper proposes an interactive, automated simulation workflow implemented in Tcl/Tk. The workflow features GUI-based testcase selection and comprehensive error handling. Experimental results show that it enables seamless testcase switching without exiting the simulation platform and provides handling for common errors, significantly reducing manual steps. This work advances automation in multi-testcase scenarios and offers a practical path toward improving simulation automation in FPGA software verification.