Time sensitive network has the characteristics of low latency, low cost, and high reliability. The Time-Aware Shaper (TAS), defined by the IEEE 802.1Qbv standard, stands as one of the critical technologies for enabling deterministic network traffic and holds a core position within the TSN protocol suite. First, by means of logical designs such as top-level architecture, workflow, and active-standby coordination, a method for implementing TAS is proposed. Second, by constructing constraints for traffic with different priorities, a deterministic scenario is designed to verify the implementation of clock synchronization and the time-aware shaper. Finally, through comparative experiments conducted before and after enabling TAS, the superiority of TSN technology over standard Ethernet in terms of low latency and low jitter is validated. The results show that, after enabling clock synchronization and gate control functions, the average delay and jitter are only about 1/20 to 1/15 of the original, which is significantly different. This provides a demonstration solution for the rapid promotion of TSN technology.