Spiking neural networks (SNNs) represent and process information using discrete spike trains, exhibiting event-driven and sparse computation characteristics and offering strong potential for energy-efficient intelligent computing. To fully exploit their low-power advantages, dedicated hardware implementation techniques and neuromorphic chips for SNNs are of significant research importance. From the perspective of hardware implementation, this paper systematically reviews the full hardware development chain of SNNs, covering neuron models, information encoding methods, network structures, and hardware architectures. The paper describes commonly used spiking neuron models and information encoding methods, discusses network structures including fully connected, convolutional, and attention-based architectures, systematically summarizes research on hardware architectures, compares the advantages and limitations of different circuit implementation technologies and computing paradigms, and analyzes current key challenges while outlining future research directions.