Network-on-Chip (NoC) has been widely adopted for on-chip communication due to its advantages of high integration, strong scalability, and low power consumption. This paper designs and implements a highly reliable dual-layer Network-on-Chip circuit. A redundant architecture is adopted via two NoC layers: one layer is used for normal data transmission, while the other layer is dedicated to timeout retransmission. To enhance anti-interference capability, triple modular redundancy (TMR) is applied to key routing control information of event packets, including flit type coding, destination router node information, and NoC ID. Meanwhile, parity check is used for the carried address and data information to ensure the correctness of data transmission. Simulation results verify that the proposed highly reliable dual-layer NoC circuit achieves correct functional behavior and excellent fault-tolerant performance.