To address the issues of high-frequency calls, large computational load, and dynamic parameter changes with subframes in the Linear Predictive Coding (LPC) analysis filter of the Opus audio encoder's SILK mode, this paper designs and implements a reconfigurable hardware accelerator based on the Zynq-7000 SoC platform. This design employs a parameterized transposed FIR fully pipelined architecture, combined with DSP48E1 resource optimization, achieving one input sample per clock cycle in steady state. To ensure data consistency during variable-length subframe switching, a Shadow/Active double-buffered parameter update mechanism is introduced, ensuring filter parameters are committed at processing frame boundaries and preventing parameter tearing within the same processing frame. An efficient hardware-software co-processing data path is constructed using AXI DMA, and hardware implementation and verification are completed according to Opus fixed-point arithmetic rules. Experimental results show that the LUT utilization rate of this design is less than 2.1% on the XC7Z100 platform, and it meets timing constraints at the target clock frequency. Under typical wideband long frame configurations, compared with the optimized libopus fixed-point C reference implementation running on ARM Cortex-A9, the algorithm core speedup reaches 9.98 times, and the average end-to-end speedup reaches 3.82×. The hardware output maintains bit-exact consistency with the software reference model. This design has low resource overhead while ensuring computational correctness, and can provide an effective hardware acceleration solution for resource-constrained embedded audio coding systems.