A Bidirectional Pin Multifunctional Multiplexing Circuit for FPGA

Zhang Xingang, Shao Chunwei, Xue Pei, Shen Xiaobo, Guan Jian

Integrated Circuits and Embedded Systems ›› 2022, Vol. 22 ›› Issue (6) : 47-50.

PDF(1320 KB)
PDF(1320 KB)
Integrated Circuits and Embedded Systems ›› 2022, Vol. 22 ›› Issue (6) : 47-50.
NEW PRODUCT & TECH

A Bidirectional Pin Multifunctional Multiplexing Circuit for FPGA

  • Zhang Xingang, Shao Chunwei, Xue Pei, Shen Xiaobo, Guan Jian
Author information +
History +

Abstract

In the paper,a circuit is proposed which is applied to the FPGA projects with multiple functional modules,so that multiple functional modules can share the bidirectional pins of FPGA.By allowing users to switch the bidirectional pins of the FPGA occupied by the functional module in real-time without obtaining the original code of the FPGA project,the application flexibility of the FPGA project after solidification is improved.By reducing the number of bidirectional pins used in FPGA,the bottleneck of the number of pins in VLSI verification applications is solved.The simulation results show that the theoretical switching delay of the circuit is up to 1 system clock.Applying this circuit to an FPGA project with 4 functional modules,the bidirectional pin occupancy rate of the FPGA can be reduced up to 75%.It’s deduced that the pin occupancy reduction range in FPGA projects containing 2~8 functional modules can reach up to 50%~87.5%.

Key words

bidirectional pin multifunctional multiplexing circuit / real-time switching function / VLSI verification

Cite this article

Download Citations
Zhang Xingang, Shao Chunwei, Xue Pei, Shen Xiaobo, Guan Jian. A Bidirectional Pin Multifunctional Multiplexing Circuit for FPGA[J]. Integrated Circuits and Embedded Systems. 2022, 22(6): 47-50

References

[1] MD Ker,Peng J J,Jiang H C.Active device under bond pad to save I/O layout for high-pin-count SoC[C]//International Symposium on Quality Electronic Design.IEEE Computer Society,2003.
[2] 胡文彬,吴剑旗,洪一.多FPGA验证平台引脚限制的解决方案[J].合肥工业大学学报(自然科学版),2010(10):1519-1522.
[3] 张俊腾,汪金辉,杨洪艳,等.IO复用电路的设计与研究[J].微电子学,2014(2):157-162.
[4] 张玥,万培元,林平分.集成电路可测性设计IO复用方法[J].半导体技术,2011,36(9):705.
[5] 黄淑燕,赖松林,赵静蕾.一种触控按键检测和LED驱动的复用IO的设计方法[J].中国集成电路,2016,25(4):53-56.
[6] 高善发.选择最佳的引脚复用技术用于多FPGA的设计分割[J].中国集成电路,2017,26(3):56.
[7] 刘云晶,刘梦影.一种32位MCU的FPGA验证平台[J].电子与封装,2020,20(1):41-47.
[8] 徐彦峰,张丽娟,谢文虎.基于FPGA的动态自重构系统原理与实现[J].电子与封装,2017(9).
[9] 刘轩.基于FPGA的多通道高速数据采集系统设计[D].北京:北京理工大学,2015:49-52.
PDF(1320 KB)

Accesses

Citation

Detail

Sections
Recommended

/