Design of SM4 Special Coprocessor Based on RISC-V Instruction Set

Wu Wenbiao, Han Yueping, Tang Daoguang

Integrated Circuits and Embedded Systems ›› 2022, Vol. 22 ›› Issue (8) : 24-28.

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Integrated Circuits and Embedded Systems ›› 2022, Vol. 22 ›› Issue (8) : 24-28.
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Design of SM4 Special Coprocessor Based on RISC-V Instruction Set

  • Wu Wenbiao1, Han Yueping1, Tang Daoguang2
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Abstract

In view of the hidden danger of imported information products and the serious shortage of RISC-V architecture products in the field of security,a fully autonomous and controllable coprocessor is designed to improve the efficiency of SM4 cryptography algorithm.The three-level pipeline structure is adopted to improve the instruction execution efficiency,and five customized instructions are extended to complete SM4 operation.The SM4 operation unit is encapsulated internally to reduce the impact on the data path and facilitate subsequent expansion.With the help of FPGA development board,verification is carried out at 50 MHz clock frequency.The results show that compared with the processor without instruction extension,the efficiency of key expansion operation is increased by 5.8 times,the efficiency of encryption operation is increased by 5.5 times,and the efficiency of decryption operation is increased by 6.4 times.The proposed scheme can significantly improve the efficiency of SM4 operation.

Key words

RISC-V / coprocessor / SM4 / custom instruction

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Wu Wenbiao, Han Yueping, Tang Daoguang. Design of SM4 Special Coprocessor Based on RISC-V Instruction Set[J]. Integrated Circuits and Embedded Systems. 2022, 22(8): 24-28

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