Based on RISC-V instruction architecture,this article implements an instruction aligning circuit.This circuit can recognize and output the correct instruction by analyzing the 32-bit instruction data passed from the I-Cache.When the address of the 32-bit instruction data is not aligned with 4-Byte,say the two least significant bits of the address is not equal to 00,this circuit automatically aligns the address of the next instruction-fetching with 4-Byte and output the signal that indicating whether the instruction is valid or invalid.When the address of the instruction data is aligned with 4-Byte,this circuit presents the instruction,the real address of this instruction,and indicates that the instruction is valid.The latency of the circuit for aligning the instruction address to 4-Byte presented in this article is 4 levels of 2-inputs logic gates,which is very useful for the front-end instruction fetch circuit of high frequency scalar processor.
Key words
RISC-V /
instruction align /
architecture /
pipeline of core
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References
[1] A Waterman,Y Lee,D A Patterson,et al.The RISCV instruction set manual: User-level ISA, version 2.0[C]//Dept. Elect. Eng. Comput. Sci.,Univ. California,Berkeley, Berkeley,CA,USA,Tech. Rep.UCB/EECS-2016-118,2014,vol.1.
[2] Zaruba F,Benini L.The Cost of Application-Class Processing: Energy and Performance Analysis of a Linux-ready 1.7GHz 64bit RISC-V Core in 22nm FDSOI Technology[J]. IEEE Transactions on Very Large Scale Integration(VLSI) Systems,2019,27(11):2629-2640.
[3] K Patsidis,D Konstantinou,C Nicopoulos,et al.A low-cost synthesizable risc-v dual-issue processor core leveraging the compressed instruction set extension[J]. Microprocess. Microsyst.,2018,61(9):1-10.
[4] Celio C,Chiu P F,Asanovic K,et al.BROOM:An open-source out-of-order processor with resilient low-voltage operation in 28 nm CMOS[J].IEEE Micro,2019(99):1.
[5] Celio C,D A Patterson,K Asanovi'c.The Berkeley Out-of-Order Machine (BOOM):An Industry-Competitive,Synthesizable, Parameterized RISC-V Processor,2015.
[6] Y Lee .A 45 nm 1.3 GHz 16.7 double-precision GFLOPS/W RISC-V processor with vector accelerators[C]//in Proc. 40th Eur. Solid State Circuits Conf. (ESSCIRC),Sep.2014:199-202.
[7] Lee Y,Zimmer B,Waterman A,et al.Raven: A 28nm RISC-V vector processor with integrated switched-capacitor DC-DC converters and adaptive clocking[C]//2015 IEEE Hot Chips 27 Symposium (HCS).IEEE, 2015.
[8] B Keller,M Cochet,B Zimmer,et al.A RISC-V processor soc with integrated power management at submicrosecond timescales in 28 nm FD-SOI[J].Solid-State Circuits,2017,52(7):1863-1875.
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