Based on MIPS32 instruction set architecture,a processor which can realize Fibonacci sequence is designed.The processor design does not use the classical five stage pipeline technology,but designs a six stage pipeline,and uses the data oriented push forward method to solve the data related problems,as well as the methods of delay transfer and branch delay slot to solve the control related problems.After the design is completed,the instruction set and function of the processor are simulated by Modelsim simulation software.The simulation results show that the instruction set and function of the processor operate normally at the clock frequency of 50 MHz.Finally,it is verified on the FPGA development board to realize the interaction between software and hardware.The verification results show that the Fibonacci sequence can be realized correctly and meet the expected design requirements.
Key words
MIPS32 /
processor /
Fibonacci sequence /
FPGA
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