Based on the application design of the independent can bus controller SJA1000 in the BasicCAN and PeliCAN modes under the two interface timing of Intel and Motorola,this paper provides a variety of application design schemes for the fields of large-scale data transmission using CAN bus,such as automobile,ship,aerospace and so on.The FPGA with model EP4CE10F17C8N is used to design the SJA1000 register reading and writing timing,data sending and receiving logic,as well as the communication with the host computer and data verification method.Through the combination of FPGA module and SJA1000 module,the Verilog program of data sending and receiving function when SJA1000 uses Intel or Motorola interface timing is designed,and the data interaction and data verification test are carried out by using CAN analyzer and host computer software.The register initialization and data sending and receiving functions of SJA1000 in BasicCAN and PeliCAN modes are realized by FPGA,and the real-time and correctness of the data are ensured when interacting with the host computer.