Design of Pipeline CPU Model Machine Based on MIPS Instruction Set

Xiao Shiwei, Li Chengkai, Yang Meina, Feng Xianghu, Sun Guocui, Du Jun

Integrated Circuits and Embedded Systems ›› 2023, Vol. 23 ›› Issue (2) : 15-18.

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Integrated Circuits and Embedded Systems ›› 2023, Vol. 23 ›› Issue (2) : 15-18.
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Design of Pipeline CPU Model Machine Based on MIPS Instruction Set

  • Xiao Shiwei, Li Chengkai, Yang Meina, Feng Xianghu, Sun Guocui, Du Jun
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Abstract

The pipeline CPU of MIPS instruction set is studied,and a design scheme of pipeline processor model machine based on MIPS is proposed.The data path of the scheme design can add instructions one by one,which is closer to the teaching practice.It adopts a five-stage pipeline architecture to realize a total of 52 instructions,including multiplication and division instructions.The teaching application method in each pipeline section is analyzed.A special exception handling module is designed for the problems related to the data and instructions of the pipeline.The model machine is tested on the EDA platform,and the test results show that the scheme meets the design requirements.

Key words

pipeline / model machine / instruction set / divider / processor

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Xiao Shiwei, Li Chengkai, Yang Meina, Feng Xianghu, Sun Guocui, Du Jun. Design of Pipeline CPU Model Machine Based on MIPS Instruction Set[J]. Integrated Circuits and Embedded Systems. 2023, 23(2): 15-18

References

[1] 向继文,刘昕,廖柏林.龙芯CPU研发与应用现状综述[J].吉首大学学报(社会科学版),2015,36(S2):126-129.
[2] 柳成,荣静.基于MIPS架构的多周期CPU设计[J].软件,2018,39(8):40-44.
[3] 刘秋菊,张光照,王仲英.基于MIPS指令集的流水线CPU设计与实现[J].实验室研究与探索,2017,36(8):148-152,172.
[4] 徐爱萍,张玉萍,涂国庆.基于VHDL之CPU设计与实践[J].实验室研究与探索,2014,33(5):120-124.
[5] 吴继明,曾碧卿.一种高效的CPU设计方法及其在计算机组成原理课程中应用[J].实验室研究与探索,2018,37(9):147-153.
[6] 李亚民.计算机组成原理与系统结构[M].北京:清华大学出版社,1999.
[7] 雷思磊.自己动手写CPU[M].北京:电子工业出版社, 2014:326-340.
[8] 严海洲.基于FPGA的MIPS单周期处理器的实现[J].电脑知识与技术,2021,17(19):5-8,13.
[9] 杨锐,黎涛.基于FPGA的流水CPU设计与实现[J].当代教育实践与教学研究,2019(24):225-226.
[10] 王帆,陈涛,张刚.基于珠算原理设计64位除法器及FPGA实现[J].科学技术与工程,2014,14(26):264-268.
[11] 王德明,骆开庆.大整数除法器硬件电路研究与实现[J].华南师范大学学报(自然科学版),2020,52(4):114-119.
[12] 黄秀荪,叶青,仇玉林.高速除法器设计及ASIC实现[J].微电子学与计算机,2008(2):133-135.
[13] 李山山,刘敬晗.利用Tomasulo算法处理数据相关的流水线CPU设计[J].实验室研究与探索,2014,33(12):90-95.
[14] 东野长磊,戚梅.一种带Cache的嵌入式CPU的设计与实现[J].微型机与应用,2010,29(14):17-19,22.
[15] 李源,马海林,何虎.基于MIPS指令集的超标量和超长指令字混合架构处理器设计[J].计算机应用研究,2016,33(6):1723-1726.
[16] 陈国志.一种自适应cache替换策略的研究与设计[J].电脑知识与技术,2011,7(5):1052-1054.
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