Smart Multi-Master Single Bus Based on FPGA

Chen Mouzhou, Zheng Xiaojun

Integrated Circuits and Embedded Systems ›› 2023, Vol. 23 ›› Issue (3) : 39-41.

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Integrated Circuits and Embedded Systems ›› 2023, Vol. 23 ›› Issue (3) : 39-41.
TECHNOLOGY REVIEW

Smart Multi-Master Single Bus Based on FPGA

  • Chen Mouzhou, Zheng Xiaojun
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Abstract

An FPGA-based intelligent multi-master single bus—Smart Multi-Master Single Bus is designed and implemented.This new type of bus can be widely used in industrial control and power system relay protection.The SM2 bus based on FPGA does not need handshake signals,adopts the mechanism of independent transceiver,transmits and receives transparently.It has the advantages of intelligence,multi-master,high speed,pin saving,area saving,and low cost,and can be connected to a variety of plug-ins and bus devices to achieve free high-speed and efficient communication between plug-ins and bus devices.

Key words

FPGA / SM2 / Multi-Master Single Bus

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Chen Mouzhou, Zheng Xiaojun. Smart Multi-Master Single Bus Based on FPGA[J]. Integrated Circuits and Embedded Systems. 2023, 23(3): 39-41

References

[1] Pango Design Suite 用户手册 V3.0,2020.
[2] Allwinner.T3 User Manual(V1.0),2016.
[3] MX3078E产品信息,2021.
[4] Zynq-7000 All Programmable SoC,2019.
[5] Clifford E Cummings.Simulation and Synthesis Techniques for Asynchronous FIFO Design[C]//SNUG 2002 (Synopsys Users Group Conference, San Jose,CA,2002) User Papers,March 2002,Section TB2,2nd paper.
[6] Philip Simpson.FPGA DESIGN-Best Practices for Team-based Design,2010.
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