In the paper,the Verilog language is used to develop a tailorable MCU based on CPLD/FPGA platform.The MCU includes a core module and some commonly used interface modules.It has 32 bits program/peripheral addressing space.With special “OR” bus structure,the instruction and peripheral interface module can be flexibly added or deleted to meet the application needs or save resources.MCU is developed with HDL language and can be transplanted between any platform CPLD/FPGA.The MCU has been used in practice and the technology is mature.
Key words
CPLD /
FPGA /
MCU /
OR bus /
tailorable /
scalability
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References
[1] MCS@51 Microcontroller Family User’S Manual,Intelcorporation,1993.
[2] 李俊,任连新,廖振雄.基于FPGA的自定义CPU架构设计[J].电子技术应用,2020,46(5):40-43,49.
[3] 张毅刚.单片机原理及应用[M].北京:高等教育出版社,2004.
[4] 刘云晶,刘梦影.一种32位MCU的FPGA验证平台[J].电子与封装,2020,20(1):43-49.
[5] 王敬华,刘武,丁国清.基于FPGA和UART的MCU总线数据采集系统设计[J].电子设计工程,2012,20(17):169-171,174.
[6] 程维,康馨宜,黄学兵.MCU的总线结构特点及其应用[J].集成电路应用,2016,33(12):38-40.