Optimization Design of SM3 Cryptographic Hash Algorithm on FPGA Platform

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Integrated Circuits and Embedded Systems ›› 2023, Vol. 23 ›› Issue (5) : 33-36.

TECHNOLOGY REVIEW

Optimization Design of SM3 Cryptographic Hash Algorithm on FPGA Platform

Zheng Jiale¹, Han Yueping¹, Tang Daoguang²

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Abstract

The basic flow of SM3 cryptographic hash algorithm is analyzed,a high-performance hardware implementation of SM3 on the field programmable gate array (FPGA) platform is designed.ARTIX-7 series chip of Xilinx is used as the core.We use a cache of 16 registers in a register group.The carry reservation adder is used to compress the critical path,which reduces the clock cycle to complete the critical path calculation in a compression function.The test results show that the throughput rate of the proposed scheme is up to 90.54 Gb/s,which is suitable for scenarios with high throughput requirements.

Key words

cryptographic hash algorithm / SM3 algorithm / FPGA / XC7A100T

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Zheng Jiale, Han Yueping, Tang Daoguang. Optimization Design of SM3 Cryptographic Hash Algorithm on FPGA Platform[J]. Integrated Circuits and Embedded Systems. 2023, 23(5): 33-36

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