Software Design Architecture for Virtual EMIF Bus of DSP

Zhu Daoshan

Integrated Circuits and Embedded Systems ›› 2023, Vol. 23 ›› Issue (5) : 37-39.

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PDF(956 KB)
Integrated Circuits and Embedded Systems ›› 2023, Vol. 23 ›› Issue (5) : 37-39.
TECHNOLOGY REVIEW

Software Design Architecture for Virtual EMIF Bus of DSP

  • Zhu Daoshan
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Abstract

To solve the problem of low speed of EMIF bus in traditional DSP+FPGA platform,a design using ZYNQ+FPGA hardware architecture is proposed,and Aurora high-speed serial bus is used to interconnect communication.By encoding the Aurora bus,the PS unit can read and write any register on the FPGA side and the data in RAM or FIFO in a software virtualization way.Compared with the traditional EMIF bus,the transmission rate is greatly improved,and the design has strong universality and portability.

Key words

virtual EMIF bus / DSP / ZYNQ / FPGA

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Zhu Daoshan. Software Design Architecture for Virtual EMIF Bus of DSP[J]. Integrated Circuits and Embedded Systems. 2023, 23(5): 37-39

References

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