Design and Verification of SoC Clock Reset Management Circuit

Li Chao, Zhao Qilin, Dai Zhaolin, Liu Lu

Integrated Circuits and Embedded Systems ›› 2023, Vol. 23 ›› Issue (6) : 8-11.

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Integrated Circuits and Embedded Systems ›› 2023, Vol. 23 ›› Issue (6) : 8-11.
TOPICAL DISCUSS

Design and Verification of SoC Clock Reset Management Circuit

  • Li Chao1, Zhao Qilin2, Dai Zhaolin1, Liu Lu1
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Abstract

In the paper,a clock and reset management circuit for system-on-chip is designed,and builds a verification platform for verification.The design integrates reset signal generation circuitry,reset synchronous release circuit,voltage reference,voltage controlled oscillator,phase-locked loop,clock gate circuit,etc.The digital circuit design is based on the 180 nm standard unit library,and a fully functional automated test platform is built based on the System Verilog language,with code coverage and functional coverage of 100%.Compared with the traditional design,all units of the circuit are internal,with high integration and high reliability.

Key words

SoC / clock management / reset management / coverage / power consumption control

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Li Chao, Zhao Qilin, Dai Zhaolin, Liu Lu. Design and Verification of SoC Clock Reset Management Circuit[J]. Integrated Circuits and Embedded Systems. 2023, 23(6): 8-11

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