High-level synthesis (HLS) tools are becoming popular in some applications such as digital signal processing and neural network,but their usability for cryptographic applications is largely unexplored.SM4 algorithms have been widely used in data encryption with increasing performance requirements for the widely used SM4 algorithm,which have the advantages of strong security,high efficiency and easy hardware implementation,and the use of hardware features for high-speed.The implementation of SM4 algorithm has become a hot topic of current research.In this paper,we use high-level synthesis(HLS) tools to synthesize C into the underlying hardware design,and propose three optimization schemes: loop unfolding,array optimization,and pipeline optimization to implement and optimize the SM4 algorithm hardware implementation.The design solutions are simulated and verified on Kintex-7 chip,and the best solution achieves a clock frequency of up to 223 MHz and a throughput of 32.10 Gb/s,which is a five-fold performance improvement over the traditional design approach.
Key words
SM4 /
high-level synthesis /
Kintex-7 /
FPGA
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