Design of SM2 Point Multiplication Coprocessor Based on RISC-V

Sun Ziting, Han Yueping, Tang Daoguang

Integrated Circuits and Embedded Systems ›› 2023, Vol. 23 ›› Issue (8) : 28-31.

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PDF(909 KB)
Integrated Circuits and Embedded Systems ›› 2023, Vol. 23 ›› Issue (8) : 28-31.
TECHNOLOGY REVIEW

Design of SM2 Point Multiplication Coprocessor Based on RISC-V

  • Sun Ziting1,2, Han Yueping1, Tang Daoguang2
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Abstract

In response to the complex structure and high computational overhead of the SM2 national secret algorithm in finite fields,the elliptic curve point multiplication and related basic operations of the SM2 national secret algorithm in binary extended domains are studied,and designs an elliptic curve point operation acceleration coprocessor based on the RISC-V instruction set.The coprocessor adopts a three-level pipeline structure,which improves computational efficiency.The processor integrates 9 custom instructions internally,which can assist the main processor supporting RISC-V to quickly complete the SM2 national security algorithm.The simulation results of Vivado show that the functions of each pipeline stage in this design are normal.The coprocessor is burned onto the Xilinx XC7A100T FPGA and runs correctly at a frequency of 200 MHz,achieving the expected goals.

Key words

RISC-V / coprocessor / multiplication point operation / binary extension domain

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Sun Ziting, Han Yueping, Tang Daoguang. Design of SM2 Point Multiplication Coprocessor Based on RISC-V[J]. Integrated Circuits and Embedded Systems. 2023, 23(8): 28-31

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