Static timing analysis mainly relies on timing models and timing constraints,which are important methods for timing verification of digital chips nowadays,where timing constraints are used to describe the designer's requirements for timing,such as clock frequency,input and output delays,etc.Correct timing constraints can shorten the chip design cycle and complete static timing analysis faster and better.For a data storage SoC chip in the multi-clock domain asynchronous design requirements,and how to correctly deal with the timing constraints exist,the paper proposes a multi-group asynchronous clock full-chip timing constraints.The false paths,multi-clock domain grouping,disable the single register multi-clock analysis settings are used to repair and optimize the design rules,build time and hold time violations.It solves the SoC memory chip static timing analysis in the timing problems,and ensures that all timing paths normally meet the timing logic function,completes the timing convergence,that meets the standards of the signed core.