Conversion interface design between RapidIO controller and network-on-chip

JU Hu; TIAN Qing; GAO Ying; HAN Yuejie; ZHOU Ying; CHEN Junru

doi:10.20193/j.ices2097-4191.2024.03.008

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Integrated Circuits and Embedded Systems ›› 2024, Vol. 24 ›› Issue (3) : 40-45. DOI: 10.20193/j.ices2097-4191.2024.03.008

Research Paper

Conversion interface design between RapidIO controller and network-on-chip

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Abstract

With the continuous improvement of embedded processor̓s performance,it is hard for the traditional parallel bus to satisfy the increasing requirement of bandwidth in embedded systems.RapidIO technology alleviates the contradiction between the traditional bus with slow development and the processor with high performance,meanwhile,network-on-chip have become the most commonly used interconnect structure in multi-core architectures.In order to realize the data interaction between RapidIO controller and network-on-chip,a conversion interface is designed,which can achieve the conversion of the RapidIO controller̓s AXI protocol to the internal packet transmission of the network-on-chip,and satisfy the needs of read/write operation of the RapidIO device.The simulation results show that the function of the conversion interface is correct and complete,and meets the design requirements.

Key words

RapidIO / network-on-chip / conversion interface

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JU Hu , TIAN Qing , GAO Ying , et al . Conversion interface design between RapidIO controller and network-on-chip[J]. Integrated Circuits and Embedded Systems. 2024, 24(3): 40-45 https://doi.org/10.20193/j.ices2097-4191.2024.03.008

References

List( Publishing order | Descend order by publishing year | Descend order by cited within ) Chart analysis

[1]	朱新忠, 王冠雄, 韦杰, 等. 一种基于Serial RapidIO标准协议的高速交换技术[J]. 航天标准化, 2020(2):8-11. ZHU X ZH, WANG G X, WEI J, et al. A high-speed switching technology based on the Serial RapidIO standard protocol[J]. Aerospace Standardization, 2020(2):8-11 (in Chinese). Cited in this article [1]

[2]	余晖冬, 龚昊龑, 王书磊. 基于FPGA+DSP架构的RapidIO接口硬件技术与实现[J]. 船电技术, 2022, 42(1):49-53. YU H D, GONG H Y, WANG SH L. RapidIO interface hardware technology and implementation based on FPGA+DSP architecture[J]. Shipbuilding Technology, 2022, 42(1):49-53 (in Chinese). Cited in this article [1]

[3]	杜加琴. 片上网络的拓扑结构设计和路由算法研究[D]. 合肥: 安徽大学, 2012. DU J Q. Topological Structure Design and Routing Algorithm Research of Network on Chip[D]. Hefei: Anhui University, 2012 (in Chinese). Cited in this article [1]

[4]	汪安民, 韩道文, 徐焱. 多核DSP和FPGA之间的高速SRIO通信[J]. 单片机与嵌入式系统应用, 2017, 17(2):4-6,22. WANG AN M, HAN D W, XU Y. High speed SRIO communication between multi-core DSP and FPGA[J]. Microcontrollers and Embedded Systems, 2017, 17(2):4-6,22 (in Chinese). Cited in this article [1]

[5]	蔡恒雨, 凤维杰, 丁上义, 等. 基于RapidIO的多DSP互联仿真实现[J]. 计算机系统应用, 2020, 29(7):95-102. CAI H Y, FENG W J, DING SH Y, et al. Implementation of Multi DSP Interconnection Simulation Based on RapidIO[J]. Computer System Application, 2020, 29(7):95-102 (in Chinese). Cited in this article [1]

[6]	王胜, 屈凌翔. 基于NoC的网络接口设计[J]. 电子与封装, 2017, 17(9):23-27. WANG SH, QU L X. Network Interface Design Based on NoC[J]. Electronics and Packaging, 2017, 17(9):23-27 (in Chinese). Cited in this article [1]

[7]	许川佩, 王纪锋, 牛军浩. NoC资源网络接口设计[J]. 电子技术应用, 2019, 45(8):118-123. XU CH P, WANG J F, NIU J H. Design of Network Interface for NoC Resources[J]. Electronic Technology Applications, 2019, 45(8):118-123 (in Chinese). Cited in this article [1]

[8]	徐玉杰, 任玉明, 张楠. 一种基于SRIO总线的接口模块设计与实现[J]. 无线互联科技, 2022, 19(6):56-58. XU Y J, REN Y M, ZHANG N. Design and Implementation of an Interface Module Based on SRIO Bus[J]. Wireless Interconnection Technology, 2022, 19(6):56-58 (in Chinese). Cited in this article [1]

[9]	李博. 基于FPGA的串行RapidIO接口的设计与实现[D]. 成都: 电子科技大学, 2017. LI B. Design and Implementation of Serial RapidIO Interface Based on FPGA[D]. Chengdu: University of Electronic Science and Technology, 2017 (in Chinese). Cited in this article [1]

[10]	何健, 兰立奇, 唐顺晨. Synopsys的SRIO controller FPGA原型验证方法[J]. 单片机与嵌入式系统应用, 2023, 23(8):24-27,31. HE J, LAN L Q, TANG SH CH. Synopsys' SRIO controller FPGA prototype verification method[J]. Application of Microcontrollers and Embedded Systems, 2023, 23(8):24-27,31 (in Chinese). Cited in this article [1]