Heterogeneous train data exchange system based on FPGA+ARM

CHEN Xiaoqi; ZHANG Liyan; LIU Yang; LI Changxian

doi:10.20193/j.ices2097-4191.2024.05.008

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Integrated Circuits and Embedded Systems ›› 2024, Vol. 24 ›› Issue (5) : 60-64. DOI: 10.20193/j.ices2097-4191.2024.05.008

Research Paper

Heterogeneous train data exchange system based on FPGA+ARM

CHEN Xiaoqi ¹ ,
ZHANG Liyan ²^,^* ,
LIU Yang ¹ ,
LI Changxian ¹

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Abstract

This paper designs and realizes a data communication interface between the host and ARM based on FPGA is designed and implemented.The PCIe interface function for interacting with the host and the FMC interface function for interacting with ARM are implemented by FPGA.The transmission performance testing of PCIe and FMC interfaces,as well as the data loop testing between the host and ARM had been completed.The test results show that the overall system design requirements have been achieved,with the PCIe 1.0 interface speed reaching 820 MB/s.

Key words

FPGA / ARM / PCIe interface / FMC interface / STM32F7

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CHEN Xiaoqi , ZHANG Liyan , LIU Yang , et al. Heterogeneous train data exchange system based on FPGA+ARM[J]. Integrated Circuits and Embedded Systems. 2024, 24(5): 60-64 https://doi.org/10.20193/j.ices2097-4191.2024.05.008

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