Design and implementation of an efficient 16-bit signed number multiplier

LI Yani, LANG Shikun, WANG Ya, SHI Ruizhi

Integrated Circuits and Embedded Systems ›› 2024, Vol. 24 ›› Issue (6) : 41-45.

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Integrated Circuits and Embedded Systems ›› 2024, Vol. 24 ›› Issue (6) : 41-45.
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Design and implementation of an efficient 16-bit signed number multiplier

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{{article.zuoZheEn_L}}. {{article.title_en}}[J]. {{journal.qiKanMingCheng_EN}}, 2024, 24(6): 41-45

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