Voltage enhancement and optimization of super junction MOS devices based on deep trench single epitaxial process

TIAN Jun; FU Zhen; ZHANG Quan; XIAO Chao; ZHANG Wenmin; WANG Yue

doi:10.20193/j.ices2097-4191.2024.06.007

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Integrated Circuits and Embedded Systems ›› 2024, Vol. 24 ›› Issue (6) : 46-54. DOI: 10.20193/j.ices2097-4191.2024.06.007

Research Paper

Voltage enhancement and optimization of super junction MOS devices based on deep trench single epitaxial process

TIAN Jun ¹^,²^,^* ,
FU Zhen ¹^,² ,
ZHANG Quan ¹^,² ,
XIAO Chao ¹^,² ,
ZHANG Wenmin ¹^,² ,
WANG Yue ¹^,²

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Abstract

In this paper,a mainstream technology for manufacturing super junction MOS (SJMOS) devices,namely the Deep Trench Single Epitaxial Process (DTSE),is introduced.And the flow and characteristics of DTSE are described in detail.Based on the charge balance principle of SJMOS,the variation of breakdown voltage (BV) under different P-pillar doping concentrations is analyzed,revealing the reasons for the low BV.A improvement solution is proposed,and its feasibility is demonstrated through the experimental verification.

Key words

super junction MOS / charge balance / deep trench / P pillar width adjustment / voltage withstand BV

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TIAN Jun , FU Zhen , ZHANG Quan , et al . Voltage enhancement and optimization of super junction MOS devices based on deep trench single epitaxial process[J]. Integrated Circuits and Embedded Systems. 2024, 24(6): 46-54 https://doi.org/10.20193/j.ices2097-4191.2024.06.007

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