This article uses agile development technology to design and improve the SM4 algorithm,and completes the implementation and verification on the Xilinx FPGA platform.In view of the shortcomings of the SM4 algorithm featuring long critical path and low throughput,a register group consisting of 32 registers is inserted into the round function calculation process as a cache area,and the pipeline method is used to shorten the critical path and optimize the S-box module structure,thus greatly improving the work efficiency.Frequency and throughput reach 340 MHz and 1.2 Gbit/s,respectively.At the same time,the new high-level hardware description language BSV is used for development,which greatly reduces the design complexity.Compared with the design using Verilog,the performance is 40% higher and the complexity is 60% lower without notable difference in hardware overhead.Compared with the earlier solution,the resource overhead is reduced by 70%,the performance is doubled,and it has higher application value.