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模态框(Modal)标题

 
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Figure/Table detail

Hardware implementation and optimization of SM3 algorithm based on BSV
LI Kexin, HAN Yueping, NIE Huaihao
Integrated Circuits and Embedded Systems, 2024, 24(10): 31-35.   DOI: 10.20193/j.ices2097-4191.2024.0028

Fig. 8 Test platform diagram
Other figure/table from this article
  • Table 1 Function list
  • Fig. 1 Overall architecture design
  • Fig. 2 Terminal calculation results
  • Fig. 3 64-stage parallel pipeline
  • Fig. 4 TT2 step calculation structure
  • Fig. 5 Single-round logic optimization
  • Fig. 6 Fill value output result
  • Fig. 7 Hash value output result
  • Table 2 Result comparison
  • Fig. 9 Operation results

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