Integrated Circuits and Embedded Systems

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Real-time efficient dense optical flow accelerator based on FPGA

FENG Yutai, XU Wenyang, CHEN Fan, WANG Jiaxing, TANG Yongming, SUN Hao

Integrated Circuits and Embedded Systems, 2025, 25(6): 78-86. DOI: 10.20193/j.ices2097-4191.2025.0021

实施工作	平台	频率/MHz	尺寸	帧率/ (f·s^-1)	吞吐量/ (Mpixels·s^-1)	LUT	FF	DSP	BRAM	功耗/W
Barranco^[9]	Virtex-4	44.0	640×480	32.0	9.80	51 879	46 122	124	244	N/A
Tomasi^[10]	Virtex-4	45.0	640×480	31.5	9.70	40 073	60 564	132	106	4.350
Smets^[18]	XC7A10T	20.0	640×480	51.0	15.70	41 853	12 599	50	43	0.024
Kunz^[19]	Altera Stratix IV	294.9	640×512	30.0	9.80	16 997	66 220	476	63	N/A
Mahalingam^[20]	Virtex-2	55.0	640×480	30.0	9.20	11 086	N/A	23	20	N/A
OpenCV	i7-1270H	2 800.0	752×480	0.6	0.21	N/A	N/A	N/A	N/A	N/A
Ours	KV260	200.0	752×480	62.0	22.38	43 499	33 274	96	187	1.069

Table 2 Hardware resource consumption and performance comparison between the proposed hardware architecture and other advanced FPGA-based implementations of optical flow algorithm

Other figure/table from this article

Fig. 1 Multi-scale pyramidal optical flow calculations
Fig. 2 Flow chart of the pyramid LK optical flow algorithm
Fig. 3 Real-time streaming hardware acceleration system with heterogeneous collaborative architecture
Fig. 4 LK pyramid data flow
Fig. 5 Schematic diagram of iterative folding pipeline architecture
Fig. 6 Image temporal gradient convolution kernel hardware
Fig. 7 Pyramid deflation module
Table 1 Error comparison between the proposed hardware architecture and OpenCV-based optical flow algorithm
Fig. 8 Overlay effect of visualization of dense optical flow field for four dataset
Table 3 Comparing hardware resource consumption for different pyramid tiers
Table 4 Performance of different resolutions under the three pyramids

模态框（Modal）标题

Figure/Table detail