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Figure/Table detail
Clock synchronization technology for CT detectors based on TDC feedback
HU Jinhui, YU Xiaodong
Integrated Circuits and Embedded Systems
, 2025, 25(
9
): 71-81. DOI:
10.20193/j.ices2097-4191.2025.0036
Fig. 5
Fine timer logic circuit
Other figure/table from this article
Fig. 1
Synchronization system architecture diagram
Fig. 2
Synchronous timing principle model
Fig. 3
Time measurement principle diagram
Fig. 4
Coarse timer logic circuit
Fig. 6
CARRY8 logic circuit
Fig. 7
CARRY8 cascade principle
Fig. 8
The data of post-implementation timing simulation
Fig. 9
Multi-layer comparator logic circuit
Table 1
Status name table
Fig. 10
State machine diagram
Table 2
Simulation sample configuration
Fig. 11
Simulation diagram of synchronous triggering
Fig. 12
Simulation diagram of synchronization delay
Fig. 13
Synchronization accuracy statistics chart
