Integrated Circuits and Embedded Systems

Design of energy-efficient op-circuit with wide-voltage based on 22 nm FD-SOI process

YANG Yanan, PEI Bingxi, ZHANG Guangda, ZHAO Xia, ZHONG Zhiyong, HE Weifeng

Integrated Circuits and Embedded Systems, 2025, 25(11): 8-14. DOI: 10.20193/j.ices2097-4191.2025.0070

流程	compile (DesignWare)	compile_ultra (DesignWare)	compile_ultra ((DesignWare-LP)
Energy DC	1.000	0.988	0.933

Table 1 Impact of different logic synthesis processes on energy efficiency

Other figure/table from this article

Fig. 1 Comparison of adder latency, power consumption and area for different architectures
Fig. 2 Comparison of multiplier latency, power consumption and area for different architectures
Fig. 3 Plot of the impact of parasitic parameters on energy efficiency
Fig. 4 Energy efficiency comparison chart for different clock cycles
Fig. 5 Comparison of area, capacitance, power consumption, and delay for four types of units
Fig. 6 Comparison chart of energy efficiency of hybrid unit combinations
Fig. 7 Comparison chart of energy efficiency at different stages
Fig. 8 Effect of cell density
Fig. 9 Distribution of each voltage domain within the module
Fig. 10 Graphic design
Fig. 11 Chip package diagram
Fig. 12 Chip test physical diagram
Fig.13 Wide voltage range test schematic
Fig. 14 Delay test schematic
Fig. 15 Energy efficiency test schematic