Figure/Table detail

Design of system memory protection unit based on bus matrix
YANG Xiaogang, ZHU Zhangmin, WEI Jinhe, HU Kai
Integrated Circuits and Embedded Systems, 2025, 25(5): 16-23.   DOI: 10.20193/j.ices2097-4191.2025.0005

区域描述信息 SDIn Core0 Core1 对应区域
Core0的核心敏感数据 0 rw- - RAM
Core0给Core1共享的数据 0/1 r- - r- - RAM
Core1给Core0共享的数据 2/1 r- - r- - RAM
Core1的核心敏感数据 2 - rw- RAM
Table 2 The description of overlap region
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