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Figure/Table detail
Design of system memory protection unit based on bus matrix
YANG Xiaogang, ZHU Zhangmin, WEI Jinhe, HU Kai
Integrated Circuits and Embedded Systems
, 2025, 25(
5
): 16-23. DOI:
10.20193/j.ices2097-4191.2025.0005
Fig. 7
The actual test of the chip
Other figure/table from this article
Fig. 1
System bus matrix
Fig. 2
Structure of memory protect unit
Table 1
The assignment of MPU logic bus master
Fig. 3
Structure of access evaluation macro
Table 2
The description of overlap region
Fig. 4
The diagram of memory overlap region
Fig. 5
The simulation of MPU
Table 3
The synthesis result of MPU
Fig. 6
The layout of the chip
Table 4
the differentpermission of the different region of Backup SRAM
Fig. 8
The result of actual chip test
