Integrated Circuits and Embedded Systems

Processing unit design for high-performance computing processors

LIU Yu, ZHANG Jie, ZHOU Le

Integrated Circuits and Embedded Systems, 2025, 25(9): 57-62. DOI: 10.20193/j.ices2097-4191.2025.0039

Fig. 4 Multiplier multiplexing

Other figure/table from this article

Fig. 1 Interconnection architecture of memory-computing convergence computational unit
Fig. 2 Structure of processing unit
Fig. 3 Multi precision hardware reuse
Fig. 5 Structure of memory unit
Fig. 6 Pipeline structure
Table 1 Timing results
Fig. 7 Critical path analysis
Table 2 Physical synthesis results
Fig. 8 Placement of computing module
Fig. 9 Power analysis of computing module
Table 3 Comparison of computational efficiency