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Figure/Table detail
Design of spatial array-based processor core
LIU Yu, ZHANG Jie, LIU Gu
Integrated Circuits and Embedded Systems
, 2025, 25(
10
): 75-81. DOI:
10.20193/j.ices2097-4191.2025.0034
Fig. 9
Mapping of bufferfly operation
Other figure/table from this article
Fig. 1
Comparison of organizational forms of computing units
Fig. 2
Comparison of organizational forms of computing units
Fig. 3
Spatial array-based core architecture
Fig. 4
Data broadcasting bus architecture
Fig. 5
MO data broadcasting
Fig. 6
MC data broadcasting
Fig. 7
Multiplexing of processing unit
Fig. 8
Example of matrix multiplication
Table 1
Logical synthesis results
Fig. 10
Placement of computing module
Fig. 11
Power analysis of computing module
Table 2
Comparison of computational efficiency
