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中文
Figure/Table detail
Research and design of multi-channel DMA controller based on AHB protocol
HONG Tengda, WANG Faxiang
Integrated Circuits and Embedded Systems
, 2025, 25(
10
): 10-16. DOI:
10.20193/j.ices2097-4191.2025.0059
Fig. 7
Simulation waveform of data processing
Other figure/table from this article
Fig. 1
Overall block diagram of DMAC
Table 1
Registers function
Fig. 2
Arbitration strategy
Fig. 3
The flow chart of data processing
Fig. 4
Verification block diagram
Fig. 5
Simulation waveform of the top
Fig. 6
Simulation waveform of the arbiter
Fig. 8
Simulation waveform of data processing (including FIFO)
Fig. 9
Simulation waveform of crossing the 1K boundary
