Design and optimization of pipelined parity check circuit for SoC memory
MA Jingbo, ZHANG Guangda, WANG Huiquan, PEI Bingxi, FANG Jian, HUANG Chenglong, LUO Hui, JIANG Yande
Integrated Circuits and Embedded Systems . 2026, (4): 26 -33 .  DOI: 10.20193/j.ices2097-4191.2025.0137