Figure/Table detail

Development and challenges of Chiplet technology
LIU Zhaoyang, REN Bolin, WANG Zedong, LV Fangxu, ZHENG Xuqiang
Integrated Circuits and Embedded Systems, 2024, 24(2): 10-22.  

In-Package D2D Connections
封装内D2D互连
Off-Package SerDes
封装外SerDes
Typical Stanards
典型值
UCIE,AIB,BOW,OPEN HBI OIF-CEI-XSR OIF-CEI-(VSR,MR,LR)
Signal Type
信号类型
Single-Ended
单端信号
Differential Paired
差分信号
Differential Paired
差分信号
Data Rate
数据速率
≤32 Gb/s 56~112 Gb/s 5~112 Gb/s
Data Format
数据格式
NRZ PAM4 NRZ(≤32 Gb/s)
PAM4(≥50 Gb/s)
Reach
传输距离
≤25 mm
(Advanced先进封装)
≤100 mm
(Standard标准封装)
≤40mm VSR(≤10 cm)
MR(≤50 cm)
LR(≤100 cm)
Architecture
架构
Mixed
混合型
Mixed
混合型
Mixed (≤32 Gb/s)
DAC/ADC DSP(≥50 Gb/s)
Clocking Scheme
时钟方案
Forward Clock
前向时钟
Clock Recovery
时钟恢复
Clock Recovery
时钟恢复
Intended Substrate
预期基板
Organic Substrate/Interposer
有机基板/互连器
Organic Substrate
有机基板
PCB
Latency
延时
Low
Medium
High
Power
功耗
Low
Medium
High
Density
密度
High
Medium
Low
Table 2 Characteristics of interconnection technology in three application scenarios
Other figure/table from this article